1. Field of the Invention
This invention relates to a PLL synthesizer circuit that operates so as to always bring an output signal frequency into conformity with a set frequency.
2. Description of the Related Art
A PLL synthesizer circuit is a negative feedback circuit that operates so as to bring a set frequency into conformity with an output signal frequency. Recently, the PLL synthesizer circuit has been used for automobile telephones, portable telephones, etc., and the time necessary to fix an output signal frequency to a set frequency must be shortened in order to reduce access time of the PLL synthesizer circuit.
An example of conventional PLL synthesizer circuits will be explained with reference to FIGS. 6 and 7 of the accompanying drawings. A quartz oscillator 1 outputs a reference clock signal CK of a natural frequency based on the oscillation of a quartz oscillation element to a reference frequency divider 2, and this reference frequency divider 2 divides the frequency of the reference clock signal CK on the basis of a set frequency, which is set from outside, and outputs a reference signal fr to a phase comparator 3. A comparison frequency divider 4 outputs a comparison signal fp to the phase comparator 3. The phase comparator 3 compares the reference signal fr with the comparison signal fp, and outputs pulse signals .phi.R and .phi.P corresponding to their frequency difference and their phase difference, respectively, to a charge pump 5.
The charge pump 5 outputs an output signal SCP on the basis of the pulse signals .phi.R, .phi.P output from the phase comparator 5, to a low-pass filter (hereinafter referred to as "LPF") 6. This output signal SCP contains a pulse component in its D.C. component. The D.C. component rises and falls with the frequency changes of the pulse signals .phi.R, .phi.P, while the pulse component changes on the basis of the phase difference of the pulse signals .phi.R, .phi.P.
The LPF 6 smoothes the output signal SCP of the charge pump 5, and outputs an output signal SLPF, from which a radio frequency (RF) component is removed, to a voltage controlled oscillator (hereinafter referred to as "VCO") 7. The VCO 7 outputs an output signal SVCO having a frequency corresponding to the voltage value of the output signal SLPF of the LPF 6 to an outside circuit and to the comparison frequency divider 4 described above. The comparison frequency divider 4 divides the frequency of the output signal SVCO of the VCO 7 and outputs it to the phase comparator 3.
The pulse signal .phi.R output from the phase comparator 3 is output as a pulse signal f.DELTA. to a lock detection circuit 8. This lock detection circuit 8 outputs a lock signal LD when a pulse width of the pulse signal f.DELTA. is below a predetermined value or when the pulse signal f.DELTA. is not output. When the output signal SVCO of the VCO 7 changes and the pulse width of the pulse signal f.DELTA. is above a predetermined value, the lock detection circuit 8 outputs an unlock signal ULD at an L level.
In the PLL synthesizer circuit having the circuit construction as described above, when a setting of the comparison signal fp, for example, is changed and its frequency is lowered from the lock state where the frequency and phase of the reference signal fr are in conformity with those of the comparison signal fp, differences occur in the frequencies and phases of the reference signal fr and the comparison signal fp as shown in FIG. 7, and then, the phase comparator 3 outputs the pulse signals .phi.R and .phi.P, and the unlock signal ULD at an L level is output. The D.C. component of the output signal SCP of the charge pump 5 changes and the pulse component develops. The voltage level of the output signal SLPF of the LPF 6 rises on the basis of the output signal SCP, and the output signal SLPF of the LPF 6 converges to a voltage level corresponding to the comparison signal fp set afresh, and the operation mode returns to the lock state.
When the frequency of the comparison signal fp of the PLL synthesizer circuit is lowered as described above, the output signal SLPF of the LPF 6 rises from V1 to V2 as indicated by a solid line in FIG. 8, for example. However, since the phase difference occurs even when the frequency of the reference signal fr is in conformity with that of the comparison signal fp, the output signal SLPF, which has risen to a point near V2, converges with V2 while repeating an over-shoot and under-shoot. Accordingly, there remains the problem that the lock-up time from the change of setting of the comparison signal fp to the rise and conversion of the output signal SLPF from V1 to V2 is long. On the other hand, the lock-up time can be shortened by reducing the time constant of the LPF 6 to reduce an over-shoot and under-shoot, but when the time constant of the LPF 6 is reduced, the pulse component contained in the output signal SCP of the charge pump 5 cannot be sufficiently eliminated, so that the frequency of the output signal SVCO of the VCO 7 becomes unstable.